The timing of different stages is important in Random Access Memory (RAM)-array design. The timing is divided into two or more different stages. One of those two or more stages is the timing between when a wordline is fired and the sense-amps are enabled where the tracking between bitcells and delay-lines is important. The post-silicon tuning advantages can be applied to other stages as well. During a read operation, a bitcell discharges one bitline of a bitline pair. After a set amount of delay, a sense amp detects the stored data value based on the voltage difference across the bitline pair. The timing of this delay is important to RAM array operation. If the delay is too long, power is wasted and performance is sacrificed. If the delay is too short, not enough differential is created, and the sense amp will not be able to reliably detect the signal (e.g., read the data from the RAM array). The ideal amount of time is a function of process, voltage, and temperature and may vary from chip to chip.